| Sl.No |
PROJECT TITLE |
DOMAIN |
| 1 |
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels. |
VLSI |
| 2 |
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology. |
VLSI |
| 3 |
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply. |
VLSI |
| 4 |
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation. |
VLSI |
| 5 |
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. |
VLSI |
| 6 |
Logical Effort for CMOS-Based Dual Mode Logic Gates. |
VLSI |
| 7 |
Area-Delay Efficient Binary Adders in QCA. |
VLSI |
| 8 |
Design and Implementation of Modified Signed-Digit Adder. |
VLSI |
| 9 |
Area–Delay–Power Efficient Carry-Select Adder. |
VLSI |
| 10 |
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes. |
VLSI |
| 11 |
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing |
VLSI |
| 12 |
Recursive Approach to the Design of a Parallel Self-Timed Adder. |
VLSI |
| 13 |
Design and Analysis of Approximate Compressors for Multiplication. |
VLSI |
| 14 |
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. |
VLSI |
| 15 |
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator. |
VLSI |
| 16 |
Logical Effort for CMOS-Based Dual Mode Logic Gates. |
VLSI |
| 17 |
Area–Delay–Power Efficient Carry-Select Adder. |
VLSI |
| 18 |
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing |
VLSI |
| 19 |
Design and Implementation of Modified Signed-Digit Adder. |
VLSI |
| 20 |
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. |
VLSI |
| 21 |
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes. |
VLSI |
