IEEE 2017-2018 VLSI
Sl.No PROJECT TITLE DOMAIN
1 Design of Power and Area Efficient Approximate Multipliers. VLSI
2 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. VLSI
3 A General Digit-Serial Architecture for Montgomery Modular Multiplication. VLSI
4 Active–Passive ΔΣ Modulator for High-Resolution and Low-Power Applications VLSI
5 A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System. VLSI
6 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications. VLSI
7 Probability-Driven Multibit Flip-Flop Integration With Clock Gating. VLSI
8 Design and Implementation of Modified Signed-Digit Adder. VLSI
9 Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. VLSI
10 Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes. VLSI
11 A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing VLSI
12 Recursive Approach to the Design of a Parallel Self-Timed Adder. VLSI
13 Design and Analysis of Approximate Compressors for Multiplication. VLSI
14 Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. VLSI
15 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator. VLSI
16 Logical Effort for CMOS-Based Dual Mode Logic Gates. VLSI
17 Area–Delay–Power Efficient Carry-Select Adder. VLSI
18 A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing VLSI
19 Design and Implementation of Modified Signed-Digit Adder. VLSI
20 Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. VLSI