| Sl.No |
PROJECT TITLE |
DOMAIN |
| 1 |
Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery. |
VLSI |
| 2 |
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits. |
VLSI |
| 3 |
Concurrent Error Detectable Carry Select Adder with Easy Testability. |
VLSI |
| 4 |
Design and Analysis of Approximate Redundant Binary Multipliers. |
VLSI |
| 5 |
Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. |
VLSI |
| 6 |
A Two-Speed, Radix-4, Serial–Parallel Multiplier. |
VLSI |
| 7 |
Formal Probabilistic Analysis of Low Latency Approximate Adders. |
VLSI |
| 8 |
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates. |
VLSI |
| 9 |
RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder. |
VLSI |
| 10 |
Design of Power and Area Efficient Approximate Multipliers. |
VLSI |
| 11 |
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing |
VLSI |
| 12 |
Recursive Approach to the Design of a Parallel Self-Timed Adder. |
VLSI |
| 13 |
Design and Analysis of Approximate Compressors for Multiplication. |
VLSI |
| 14 |
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. |
VLSI |
| 15 |
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator. |
VLSI |
| 16 |
Logical Effort for CMOS-Based Dual Mode Logic Gates. |
VLSI |
| 17 |
Area–Delay–Power Efficient Carry-Select Adder. |
VLSI |
| 18 |
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing |
VLSI |
| 19 |
Design and Implementation of Modified Signed-Digit Adder. |
VLSI |
| 20 |
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. |
VLSI |
